1. Field of the Invention
The present invention relates to a semiconductor integrated circuit capable of operating at a high speed at a low voltage, and in particular to a semiconductor integrated circuit using a pass transistor logic circuit including a combination of FET pass transistor gates.
2. Description of the Related Art
A conventional pass transistor logic circuit is disclosed in Low-Voltage/Low-Power Integrated Circuits and Systems, IEEE PRESS, pp. 202-204 and Japanese Laid-Open Publication No. 10-135814.
FIG. 16 shows an example of a conventional pass transistor logic circuit. The pass transistor logic circuit shown in FIG. 16 includes a buffer circuit 59 and a pass transistor network 60. The pass transistor network 60 is connected to the buffer circuit 59 through a connection line 50a. 
The buffer circuit 59 includes a CMOS inverter 59a including a P-type MOSFET 59b and an N-type MOSFET 59c, and a pull-up P-type MOSFET 59d. A source of the P-type MOSFET 59b is connected to a power supply line 50, and a drain and a gate of the P-type MOSFET 59b are respectively connected to a drain and a gate of the N-type MOSFET 59c. A source of the N-type MOSFET 59a is connected to a GND line 51 (i.e., grounded). The gate of the P-type MOSFET 59b and the drain of the N-type MOSFET 59c act as an input terminal 50c, and the drain of the P-type MOSFET 59b and the gate of the N-type MOSFET 59c act as an output terminal 58. A source of the P-type MOSFET 59d is connected to the power supply line 50, and a gate and a drain of the P-type MOSFET 59d are respectively connected to the output terminal 58 and the input terminal 50c. 
The pass transistor network 60 includes four N-type MOSFETs 52, 53, 56 and 57 which form a pass transistor tree. A drain of the N-type MOSFET 52 is connected to a drain of the N-type MOSFET 57. A gate and a source of the N-type MOSFET 57 are respectively connected to a control input terminal 57a and an input terminal 55b. A gate of the N-type MOSFET 52 is connected to a control input terminal 52a. A source of the N-type MOSFET 52 is connected to a drain of the N-type MOSFET 53 and also to a drain of the N-type MOSFET 56. Similarly, a gate and a source of the N-type MOSFET 53 are respectively connected to a control input terminal 53a and an input terminal 54a. A gate and a source of the N-type MOSFET 56 are respectively connected to a control input terminal 56a and an input terminal 55b. 
Signals which are input to an input terminal 54a, 55a and 55b respectively connected to the sources of the three N-type MOSFETs 53, 56 and 57 are processed with a prescribed logic operation based on a signal applied to the control input terminals 52a, 53a, 56a and 57a. The resultant signal is output to the input terminal 50c of the CMOS inverter 59a of the buffer circuit 59 through the connection line 50a from a connection point 50b between the drains of the two N-type MOSFETs 52 and 57. The signal is amplified and waveform-shaped by the CMOS inverter 59a and output from the output terminal 58 of the CMOS inverter 59a to an external circuit.
The pass transistor network 60 shown in FIG. 16 includes a two-stage pass transistor tree, but a more complicated logic circuit includes a pass transistor tree of more than two stages. FIG. 17 shows an example of such a pass transistor network 80.
FIG. 17 shows a pass transistor logic circuit including the pass transistor network 80 including six N-type MOSFETs 61m through 66m connected in series, and a buffer circuit 68 including a CMOS inverter and a pull-up P-type MOSFET, like the buffer circuit 59. The six N-type MOSFETs 61m through 66m are connected in series through connection of a drain and a source of two adjacent MOSFETs. A drain of the sixth-stage N-type MOSFET 66m is connected to an input terminal of the buffer circuit 68 (i.e., an input terminal of the CMOS inverter). The pass transistor network 80 includes control input terminals 61 through 66 and an input terminal 67. The control input terminals 61 through 66 are respectively connected to gate terminals of the N-type MOSFETs 61m through 66m. The input terminal 67 is connected to a source of the N-type MOSFET 61m. 
A signal which is input to the input terminal 67 is processed with a prescribed logic operation based on signals applied to the control input terminals 61 through 66. The resultant signal is output from the drain of the N-type MOSFET 66m to the input terminal of the CMOS inverter of the buffer circuit 68. The signal is amplified and waveform-shaped by the CMOS inverter and output from an output terminal 69 of the buffer circuit 68, the output terminal 69 being connected to an output terminal of the CMOS inverter.
FIG. 18 is a graph illustrating a delay characteristic of an input/output voltage of the pass transistor logic circuit shown in FIG. 17. The horizontal axis represents time, and the vertical axis represents the input/output voltage. An input voltage In-68 shown in FIG. 18 represents a voltage of a signal which is input to the input terminal 67 of the pass transistor network 80. The input voltage In-68, which periodically changes from a LOW level to a HIGH level, passes through the N-type MOSFETs 61m through 66m connected in series and then is input to the input terminal of the buffer circuit 68. The signal is then output to the output terminal 69 of the buffer circuit 68. An output voltage Out-68 represents a voltage of the signal which is output to the output terminal 69. The input voltage In-68 increases from the ground level GND to the supply voltage level Vdd over-time. The output voltage Out-68 is obtained by inversion performed by the CMOS inverter, and thus decreases from the supply voltage level Vdd to a level representing an OFF state.
As described above, the pass transistor network 80 includes six N-type MOSFETs 61m through 66m. Therefore, when the input voltage of the buffer circuit 68 changes from the LOW level to the HIGH level, the voltage level does not rise to the supply voltage level Vdd but rises only to a voltage level which is lower than the supply voltage level Vdd by a threshold voltage of the N-type MOSFETs. The input voltage In-68 increases over-time, and the drain-source voltage and the gate-source voltage of each of the N-type MOSFETs 61m through 66m decrease. Therefore, the amplification degree of each of the Ntype MOSFETs 61m through 66m approaches an OFF region (saturation region), and the gradient of rise of the input voltage of the buffer circuit 68 from the LOW level to the HIGH level is slower. When the input voltage In-68 becomes Vi at time t0, the output voltage Out-68 at the output terminal 69 decreases from the supply voltage level Vdd by a threshold voltage of the P-MOSFET to a level Vo. Therefore, the P-MOSFET is turned ON, and the input voltage In-68 is raised to the supply voltage level Vdd (i.e., pulled up). The pulled-up voltage In-68 is input to the buffer circuit 68, and a signal having the output voltage Out-68 is output from the output terminal 69 of the buffer circuit 68.
Since a signal which is input to the input terminal 67 passes through the six N-type MOSFETs 61m through 66m connected in series, the signal rises from a LOW level to a HIGH level very slowly and thus the propagation time of the signal is increased. In the buffer circuit 68 having a CMOS inverter, when the rise of the input signal from a LOW level to a HIGH level is slow, a significant delay is caused in the signal propagation time before the input voltage In-68 reaches the signal inversion level (threshold level). In addition, since the transition time before the input voltage In-68 reaches the signal inversion level is excessively long, a large shoot-through current flows, resulting in an increase in the current consumption. In the case where an input signal sent from the pass transistor network 80 to the buffer circuit 68 has an excessively low level, the signal inversion level of the CMOS inverter cannot be fulfilled and as a result, the operation of the buffer circuit 68 may stop.
The N-type MOSFETs 61m through 66m and the pull-up P-type MOSFET and the CMOS inverter included in the buffer circuit 68 are designed using a commonly used bulk process.
FIG. 19 shows an exemplary structure of the CMOS inverter included in the buffer circuit 68. The CMOS inverter includes a semiconductor substrate 81, an Ntype well layer 82 included in a P-type MOSFET 81a, and a P-type well layer 83 included in an N-type MOSFET 81b adjacent to the P-type MOSFET 81a. The N-type well layer 82 and the P-type well layer 83 are provided so as to have a surface thereof at the same level. In the N-type well layer 82, a P-type layer 84 acting as a source region of the P-type MOSFET 81a and a P-type layer 86 acting as a drain region of the P-type MOSFET 81a are provided so as to have a surface thereof at the same level as the surface of the N-type well layer 82. A channel region 85 is between the P-type layer 84 and the P-type layer 86. In the P-type well layer 83 adjacent to the N-type well layer 82, an N-type layer 87 acting as a drain region of the N-type MOSFET 81b and an N-type layer 89 acting as a source region of the N-type MOSFET 81b are provided so as to have a surface thereof at the same level as the surface of the P-type well layer 83. A channel region 88 is between the N-type layer 87 and the N-type layer 89. The N-type well layer 82 and the P-type well layer 83 are covered with a continuous oxide layer 92. In the oxide layer 92, a gate electrode 90 of the P-type MOSFET 81a is provided above the channel region 85. Also in the oxide layer 92, a gate electrode 91 of the N-type MOSFET 81b is provided above the channel region 88.
According to the commonly used bulk process, devices such as, for example, a P-type MOSFET and an N-type MOSFET are provided so as to include a P-type well layer and an N-type well layer. Therefore, a large junction capacitance is generated in the source region and the drain region of each device. The large junction capacitance increases the current consumption and the delay time in signal propagation during the operation of each device. Similarly, according to the commonly used bulk process, the threshold voltage of the N-type MOSFET cannot be set to be lower than a prescribed level, the logical amplitude is reduced by the above-described voltage drop from the supply voltage level Vdd, which prevents realization of a low voltage operation.
Japanese Laid-Open Publication No. 10-135814 discloses an example of a pass transistor logic circuit including a pass transistor network, which is designed using an SOI (Silicon on Insulator) technology, and a buffer circuit.
FIGS. 20A and 20B each show an example of a pass transistor logic circuit disclosed in Japanese Laid-Open Publication No. 10-135814.
FIG. 20A shows a pass transistor logic circuit including an SOI-NMOS pass transistor network 71 and a buffer circuit 72 including CMOS inverters 72a and 72b. The SOI-NMOS pass transistor network 71 includes two N-type MOSFETs 71a and 71b having gates and bodies (a body corresponding to a substrate of a MOS structure using a bulk substrate) which are connected to each other as described below. The SOI-NMOS pass transistor network 71 determines logic synthesis.
The CMOS inverter 72a includes a P-type MOSFET 72c and an N-type MOSFET 72d. Gates of the P-type MOSFET 72c and the N-type MOSFET 72d are connected to each other, and bodies of the P-type MOSFET 72c and the N-type MOSFET 72d are connected to each other. The CMOS inverter 72b includes a P-type MOSFET 72e and an N-type MOSFET 72f. Gates of the P-type MOSFET 72e and the N-type MOSFET 72f are connected to each other, and bodies of the P-type MOSFET 72e and the N-type MOSFET 72f are connected to each other.
As described above, the SOI-NMOS pass transistor network 71 includes two N-type MOSFETs 71a and 71b which are connected in parallel through drains thereof. Sources of the N-type MOSFETs 71a and 71b are respectively connected to input terminals 75a and 75b of the SOI-NMOS pass transistor network 71. Gates of the N-type MOSFETs 71a and 71b are connected to an input terminal 75c of the SOI-NMOS pass transistor network 71. The drains of the N-type MOSFETs 71a and 71b which are connected to each other are respectively connected to an output terminal 76a and a complementary output terminal 76b of the SOI-NMOS pass transistor network 71.
The output terminal 76a of the SOI-NMOS pass transistor network 71 is connected to an input terminal of the CMOS inverter 72a. The complementary output terminal 76b of the SOI-NMOS pass transistor network 71 is connected to the input terminal of the CMOS inverter 72b. 
FIG. 20B shows a pass transistor logic circuit including an SOI-NMOS pass transistor network 71 and a body-controlled PMOS feedback type buffer circuit 73. The SOI-NMOS pass transistor network 71 has the same structure as that shown in FIG. 20A.
The buffer circuit 73 includes a pair of P-type MOSFETs 73a and 73c and a pair of N-type MOSFETs 73b and 73d. A body of the P-type MOSFET 73a is connected to an output terminal 76a of the SOI-NMOS pass transistor network 71, and a body of the P-type MOSFET 73c is connected to a complementary output terminal 76b of the SOI-NMOS pass transistor network 71. Sources of the P-type MOSFETs 73a and 73c are connected to a power supply line, and drains of the P-type MOSFETs 73a and 73c are respectively connected to drains of the N-type MOSFETs 73b and 73d. Sources of the N-type MOSFETs 73b and 73d are grounded. A gate of the P-type MOSFET 73a is connected to a connection point between the P-type MOSFET 73a and the N-type MOSFET 73d, and a gate of the P-type MOSFET 73c is connected to a connection point between the P-type MOSFET 73a and the N-type MOSFET 73b. A gate of the N-type MOSFET 73b is connected to a body of the P-type MOSFET 73a and also connected to the output terminal 76a. A gate of the N-type MOSFET 73d is connected to a body of the P-type MOSFET 73c and also connected to the complementary output terminal 76b. Connection points between the P-type MOSFETs 73a and 73c respectively act as an output terminal or a complementary output terminal, or vice versa, of the buffer circuit 73.
The buffer circuits 72 and 73 respectively shown in FIGS. 20A and 20B control the body potentials of the P-type MOSFETs 73a and 73c and the N-type MOSFETs 73b and 73d, which are partially depleted SOI devices, so as to control the threshold voltage. Thus, the buffer circuits 72 and 73 suppress a shoot-through current flowing therein so as to reduce the current consumption.
FIG. 21 shows an exemplary CMOS inverter using an SOI technique.
The CMOS inverter includes a semiconductor substrate 93, and an oxide layer 94 having a prescribed thickness provided on the semiconductor substrate 93. In the oxide layer 94, P-type layers 95 and 97 are provided with a prescribed distance therebetween. N-type layers 98 and 100 are also provided in the oxide layer 94 with a prescribed distance therebetween. The P-type layers 95 and 97 and the N-type layers 98 and 100 are provided so as to have a surface thereof at the same level as a surface of the oxide layer 94. The P-type layers 95 and 97 are included in a P-type MOSFET 93a, and the N-type layers 98 and 100 are included in the N-type MOSFET 93b. A channel region formed of an N-type layer 96 between the P-type layers 95 and 97 acts as a body of the P-type MOSFET 93a, and a channel region formed of a P-type layer 99 between the N-type layers 98 and 100 acts as a body of the N-type MOSFET 93b. The N-type layer 96 and the P-type layer 99 also have a surface at the same level of the surface of the oxide layer 94.
The P-type layers 95 and 97, the N-type layer 96, the N-type layers 98 and 100, the P-type layer 99, and the oxide layer 94 are covered with a continuous oxide layer 103. In the oxide layer 103, a gate electrode 101 of the P-type MOSFET 93a is provided above the N-type layer 96. Also in the oxide layer 103, a gate electrode 102 of the N-type MOSFET 93b is provided above the P-type layer 99.
In such a CMOS inverter structure designed using the SOI technique, the P-type MOSFET 93a and the N-type MOSFET 93b are separated from the semiconductor substrate 93 by a prescribed distance corresponding to the thickness of the oxide layer 94. Therefore, a large junction capacitance, which is generated in a CMOS inverter designed by the bulk process, is not generated. The MOSFETs designed using the SOI technique can have a higher ratio between the ON current magnitude and the OFF current magnitude than in the MOSFETs designed by the bulk process. Therefore, the MOSFETs designed using the SOI technique have a steep sub-threshold characteristic and thus can be driven at a lower threshold voltage and have a shorter response time to a signal. A pass transistor logic circuit including devices designed with the SOI technique is capable of low voltage driving and high speed operation.
However, the buffer circuits 72 and 73 shown in FIGS. 20A and 20B have the following problems.
The buffer circuit 72 shown in FIG. 20A has the problems of, for example, the signal delay time being long and the current consumption being not reduced, like in the case of the pass transistor logic circuit shown in FIG. 17 designed by the bulk process.
The pass transistor logic circuit including the body-controlled PMOS feedback type buffer circuit 73 shown in FIG. 20B allows a signal exceeding the signal inversion level to be pulled up due to the circuit operation of the buffer circuit 73 and therefore can reduce the current consumption by suppressing the shoot-through current. However, the non-sharp shape of the signal waveform which is caused by the delay of the signal in the multi-stage pass transistor network cannot be alleviated.
A semiconductor integrated circuit according to the present invention includes a plurality of logical elements connected in series or parallel, the plurality of logical elements including a semiconductor substrate and an insulating layer provided on the semiconductor substrate; and a buffer circuit connected between a logical element group including at least two of the plurality of logical elements and another logical element group including at least two of the plurality of logical elements.
In one embodiment of the invention, the logical elements are N-type MOSFETs.
In one embodiment of the invention, the logical elements are P-type MOSFETs.
In one embodiment of the invention, the logical elements are CMOS transmission gates each including a P-type MOSFET and an N-type MOSFET.
In one embodiment of the invention, the buffer circuit is a CMOS inverter including a P-type MOSFET and an N-type MOSFET.
In one embodiment of the invention, the buffer circuit includes a P-type MOSFET and a CMOS inverter including a P-type MOSFET and an N-type MOSFET, a source of the P-type MOSFET is connected to a power supply line, and a drain and a gate of the P-type MOSFET are respectively connected to an input terminal and an output terminal of the CMOS inverter.
In one embodiment of the invention, the buffer circuit includes an N-type MOSFET and a CMOS inverter including a P-type MOSFET and an N-type MOSFET, a source of the N-type MOSFET is connected to a ground line, and a drain and a gate of the N-type MOSFET are respectively connected to an input terminal and an output terminal of the CMOS inverter.
In one embodiment of the invention, a threshold voltage of the P-type MOSFET is set to be a high level.
In one embodiment of the invention, a threshold voltage of the P-type MOSFET is set to be a high level.
In one embodiment of the invention, a threshold voltage of the N-type MOSFET is set to be a high level.
In one embodiment of the invention, a threshold voltage of the N-type MOSFET is set to be a high level.
In one embodiment of the invention, the buffer circuit is a non-inverter type buffer circuit including two inverter circuits connected in series.
In one embodiment of the invention, one of the inverter circuits of the non-inverter type buffer circuit is a buffer circuit including a CMOS inverter including a P-type MOSFET and an N-type MOSFET.
In one embodiment of the invention, one of the inverter circuits of the non-inverter type buffer circuit is a buffer circuit including a first P-type MOSFET and a CMOS inverter including a second P-type MOSFET and an N-type MOSFET, a source of the first P-type MOSFET is connected to a power supply line, and a drain and a gate of the first P-type MOSFET are respectively connected to an input terminal and an output terminal of the CMOS inverter.
In one embodiment of the invention, one of the inverter circuits of the non-inverter type buffer circuit is a buffer circuit including a first N-type MOSFET and a CMOS inverter including a P-type MOSFET and a second N-type MOSFET, a source of the first N-type MOSFET is connected to a ground line, and a drain and a gate of the first N-type MOSFET are respectively connected to an input terminal and an output terminal of the CMOS inverter.
Thus, the invention described herein makes possible the advantages of providing a semiconductor integrated circuit for suppressing non-sharpness of the waveform of a signal propagated through a pass transistor logic circuit so as to shorten the delay time.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.